In pipelined processors, a data hazard occurs when: MCQ with Answer and Explanation

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In pipelined processors, a data hazard occurs when:

A. Clock speed is too high

B. Branches are predicted wrong

C. An instruction depends on the result of a previous instruction still in pipeline

D. Cache miss happens

Answer: Option C

Solution (By JKSSB Mock Tests)

Forwarding or stalls are used to resolve them.

This question belongs to: Computer CPU (Central Processing Unit)

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Practice More CPU (Central Processing Unit) Questions

Question #1

AVX instructions extend:

A. Vector processing capabilities

B. Memory addressing

C. Basic arithmetic only

D. Control unit functions

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Correct Answer: Option A

Explanation:
Advanced Vector Extensions for wider SIMD.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

The ROB (Reorder Buffer) size affects:

A. Power only

B. How many instructions can be in flight

C. Address bus

D. Cache size

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Correct Answer: Option B

Explanation:
Larger ROB supports more out-of-order execution.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

The Memory Buffer Register (MBR) holds:

A. Data being transferred to or from memory

B. Control signals

C. Address only

D. Next program address

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Correct Answer: Option A

Explanation:
It acts as a buffer for data movement between CPU and memory.

This question belongs to: Computer CPU (Central Processing Unit)

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