In pipelined processors, a data hazard occurs when: MCQ with Answer and Explanation

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In pipelined processors, a data hazard occurs when:

A. Clock speed is too high

B. Branches are predicted wrong

C. An instruction depends on the result of a previous instruction still in pipeline

D. Cache miss happens

Answer: Option C

Solution (By JKSSB Mock Tests)

Forwarding or stalls are used to resolve them.

This question belongs to: Computer CPU (Central Processing Unit)

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Practice More CPU (Central Processing Unit) Questions

Question #1

Neural Processing Unit (NPU) in CPUs is for:

A. Display

B. Accelerating AI and machine learning tasks

C. Basic arithmetic

D. Storage

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Correct Answer: Option B

Explanation:
Specialized for tensor operations in AI.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

The exception handling in CPU involves:

A. Ignoring errors

B. Precise interrupts and state saving

C. Cache flush only

D. ALU reset

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Correct Answer: Option B

Explanation:
For errors and interrupts.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

The von Neumann architecture features:

A. Shared memory for data and instructions

B. Separate memory for data and instructions

C. No CPU

D. Only quantum processing

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Correct Answer: Option A

Explanation:
In von Neumann model, instructions and data share the same memory space.

This question belongs to: Computer CPU (Central Processing Unit)

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