The issue stage in pipeline: MCQ with Answer and Explanation

Question

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The issue stage in pipeline:

A. Writes results

B. Fetches from memory

C. Dispatches instructions to execution units

D. Decodes only

Answer: Option C

Solution (By JKSSB Mock Tests)

Assigns to appropriate functional units.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

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Apple Silicon like M-series uses:

A. No CPU

B. ARM-based architecture

C. x86 only

D. CISC heavy

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Correct Answer: Option B

Explanation:
Custom ARM chips for Macs.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

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The coherence directory is used in:

A. Large scale multi-core systems

B. Mobile only

C. Single core

D. Cache less designs

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Correct Answer: Option A

Explanation:
For directory-based coherence.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

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Cache memory is placed between:

A. CPU and RAM

B. Input and Output devices

C. ALU and CU

D. RAM and Hard Disk

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Correct Answer: Option A

Explanation:
Cache provides faster access to frequently used data between CPU and main memory.

This question belongs to: Computer CPU (Central Processing Unit)

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