Why is cache memory constructed using Static RAM (SRAM) instead of Dynamic RAM (DRAM)?
A. SRAM requires complex capacitor discharge routines.
B. SRAM does not need refresh cycles, allowing for significantly higher operation speeds.
C. SRAM is much cheaper to scale up in size.
D. SRAM is non-volatile and preserves data when power is disconnected.
Answer: Option B
Solution (By JKSSB Mock Tests)
SRAM is substantially faster than DRAM because it uses a multi-transistor configuration (flip-flops) that retains state instantly without periodic electrical refreshing.
Explanation:
A parity bit is an extra bit added to data to detect errors (single-bit errors) in memory. It is used in some RAM modules for error detection.
Explanation:
A memory controller with multiple channels can distribute traffic to increase bandwidth, combine capacities, and select channels based on addressing.
Explanation:
A memory map defines the layout of physical memory, including the address ranges assigned to different types of memory (RAM, ROM, I/O devices) in a system.
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