Instruction level parallelism (ILP) is exploited by: MCQ with Answer and Explanation

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Instruction level parallelism (ILP) is exploited by:

A. Single core only

B. Pipelining and superscalar designs

C. Memory

D. Software only

Answer: Option B

Solution (By JKSSB Mock Tests)

Hardware techniques maximize parallel instruction execution.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

CISC stands for:

A. Complex Instruction Set Computer

B. Central Integrated System Computer

C. Control Instruction Set Computer

D. Cache Instruction Set Computer

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Correct Answer: Option A

Explanation:
CISC uses complex multi-step instructions.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

The coherence protocol like MESI is for:

A. Cache coherence in multi-core systems

B. Instruction fetch

C. Power saving

D. ALU operations

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Correct Answer: Option A

Explanation:
Maintains consistent data across caches.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

3D V-Cache technology by AMD increases:

A. Clock speed

B. Power draw

C. Core count

D. L3 cache capacity using stacked design

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Correct Answer: Option D

Explanation:
It significantly boosts cache for gaming and workloads.

This question belongs to: Computer CPU (Central Processing Unit)

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