Interrupt handling is managed by: MCQ with Answer and Explanation

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Interrupt handling is managed by:

A. ALU

B. Registers only

C. Control Unit

D. External devices only

Answer: Option C

Solution (By JKSSB Mock Tests)

CU responds to interrupts by saving state and handling requests.

This question belongs to: Computer CPU (Central Processing Unit)

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Practice More CPU (Central Processing Unit) Questions

Question #1

A higher clock speed with lower IPC may perform:

A. Differently depending on workload

B. Same as low clock high IPC

C. Always better

D. Worse always

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Correct Answer: Option A

Explanation:
Balance is key.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

AVX-512 refers to:

A. Cache level

B. Power management

C. Core count

D. 512-bit vector instruction extensions

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Correct Answer: Option D

Explanation:
It enables wider SIMD operations.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

Heterogeneous computing typically combines:

A. Software layers

B. Only identical cores

C. Memory modules

D. CPU and GPU or specialized accelerators

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Correct Answer: Option D

Explanation:
It optimizes different workloads.

This question belongs to: Computer CPU (Central Processing Unit)

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