Multi-level cache hierarchy reduces: MCQ with Answer and Explanation

Question

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Multi-level cache hierarchy reduces:

A. Core count

B. Instruction set

C. Average memory access time

D. Clock frequency

Answer: Option C

Solution (By JKSSB Mock Tests)

Exploits locality.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

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Which is true about embedded CPUs?

A. Many threads

B. Large cache priority

C. High performance gaming

D. Focus on real-time response and low power

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Correct Answer: Option D

Explanation:
Used in IoT and appliances.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

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The opcode fetch is part of:

A. Write-back stage

B. Execution stage

C. Instruction fetch stage

D. Memory stage

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Correct Answer: Option C

Explanation:
First step in processing an instruction.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

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Guard pages and stack canaries are:

A. Software security features supported by CPU

B. Power features

C. Hardware only

D. Unrelated to CPU

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Correct Answer: Option A

Explanation:
Prevent exploits.

This question belongs to: Computer CPU (Central Processing Unit)

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