The bus cycle includes: MCQ with Answer and Explanation

Question

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The bus cycle includes:

A. Register transfer

B. Address, data, and control phases

C. ALU operations only

D. Instruction decode

Answer: Option B

Solution (By JKSSB Mock Tests)

For communication with memory.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

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Back-end focuses on:

A. Fetching

B. Decoding

C. Addressing

D. Execution and retirement

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Correct Answer: Option D

Explanation:
Carrying out and completing instructions.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

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The predicate register in some ISAs enables:

A. ALU bypass

B. No conditional

C. Guarded execution

D. Memory only

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Correct Answer: Option C

Explanation:
Avoids branches.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

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The load queue manages:

A. Writes only

B. Pending memory reads

C. ALU

D. Control

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Correct Answer: Option B

Explanation:
For memory operations in pipeline.

This question belongs to: Computer CPU (Central Processing Unit)

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