The latency of L1 cache is typically: MCQ with Answer and Explanation

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The latency of L1 cache is typically:

A. Few clock cycles

B. Infinite

C. Hundreds of cycles

D. Same as RAM

Answer: Option A

Solution (By JKSSB Mock Tests)

Very low latency for fast access.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

RISC-V is an example of:

A. Proprietary CISC design

B. Graphics processor

C. Open-source Instruction Set Architecture

D. Memory controller

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Correct Answer: Option C

Explanation:
It is a royalty-free RISC ISA.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

The latency of register access is:

A. Variable by design

B. Same as main memory

C. Hundreds of cycles

D. 1 clock cycle or less

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Correct Answer: Option D

Explanation:
Registers are the fastest storage.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

The von Neumann architecture features:

A. Shared memory for data and instructions

B. No CPU

C. Separate memory for data and instructions

D. Only quantum processing

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Correct Answer: Option A

Explanation:
In von Neumann model, instructions and data share the same memory space.

This question belongs to: Computer CPU (Central Processing Unit)

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