A. To enforce memory ordering in concurrent programming
B. To reduce memory usage
C. To separate memory regions for security
D. To increase memory speed
Answer: Option A
Solution (By JKSSB Mock Tests)
A memory fence is a barrier instruction that ensures all preceding memory operations are completed before subsequent ones, maintaining consistency in multi-threaded environments.
Explanation:
SRAM (Static RAM) uses a latching circuitry design (typically 6 transistors per cell forming cross-coupled inverters) to maintain its state as long as power is applied.
Explanation:
TBW (Terabytes Written) is an endurance metric that specifies the total cumulative amount of data an SSD can safely write before flash memory cell degradation risk increases.
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