The decode stage may involve: MCQ with Answer and Explanation

Question

Share Report Error

The decode stage may involve:

A. Complex decoding for variable length instructions

B. ALU computation

C. Simple fixed length only

D. No decoding

Answer: Option A

Solution (By JKSSB Mock Tests)

In x86 especially.

This question belongs to: Computer CPU (Central Processing Unit)

Request complete Subject PDF

Discuss this Question (0)

No comments yet. Be the first to start the discussion!

Practice More CPU (Central Processing Unit) Questions

Question #1

Share Report

The operand in an instruction can be located in:

A. Only ALU

B. Only memory

C. CU only

D. Register, memory, or immediate

View Answer & Solution Discuss

Get Complete Subject PDF for Computer

Correct Answer: Option D

Explanation:
Different addressing modes specify operand location.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

Share Report

Multi-level cache hierarchy reduces:

A. Clock frequency

B. Average memory access time

C. Core count

D. Instruction set

View Answer & Solution Discuss

Get Complete Subject PDF for Computer

Correct Answer: Option B

Explanation:
Exploits locality.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

Share Report

Power gating technique turns off:

A. Cache only

B. Unused circuit blocks to save leakage power

C. ALU permanently

D. All cores simultaneously

View Answer & Solution Discuss

Get Complete Subject PDF for Computer

Correct Answer: Option B

Explanation:
It improves energy efficiency.

This question belongs to: Computer CPU (Central Processing Unit)

Explore All CPU (Central Processing Unit) MCQs