The fetch width in superscalar CPUs refers to: MCQ with Answer and Explanation

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The fetch width in superscalar CPUs refers to:

A. Data bus width

B. Register size

C. Number of instructions fetched per cycle

D. Cache line

Answer: Option C

Solution (By JKSSB Mock Tests)

Affects instruction throughput.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

The latency of L1 cache is typically:

A. Infinite

B. Few clock cycles

C. Hundreds of cycles

D. Same as RAM

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Correct Answer: Option B

Explanation:
Very low latency for fast access.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

The issue stage in pipeline:

A. Decodes only

B. Writes results

C. Dispatches instructions to execution units

D. Fetches from memory

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Correct Answer: Option C

Explanation:
Assigns to appropriate functional units.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

3D stacking in CPUs improves:

A. Clock speed only

B. Manufacturing simplicity

C. Power consumption negatively

D. Cache density and bandwidth

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Correct Answer: Option D

Explanation:
Like AMD's 3D V-Cache.

This question belongs to: Computer CPU (Central Processing Unit)

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