The ITLB caches: MCQ with Answer and Explanation

Question

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The ITLB caches:

A. Instruction address translations

B. ALU results

C. Data translations

D. Branch history

Answer: Option A

Solution (By JKSSB Mock Tests)

Separate from DTLB.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

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The shadow registers or checkpointing is for:

A. Normal operations

B. Storage

C. Speculative execution recovery

D. Display

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Correct Answer: Option C

Explanation:
To rollback on mis-speculation.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

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In pipelined processors, a data hazard occurs when:

A. Branches are predicted wrong

B. An instruction depends on the result of a previous instruction still in pipeline

C. Clock speed is too high

D. Cache miss happens

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Correct Answer: Option B

Explanation:
Forwarding or stalls are used to resolve them.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

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Zen 5 is an example of:

A. Intel design

B. GPU architecture

C. ARM core

D. AMD CPU microarchitecture

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Correct Answer: Option D

Explanation:
It powers recent Ryzen processors.

This question belongs to: Computer CPU (Central Processing Unit)

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