The status of 'dirty' bit in cache indicates: MCQ with Answer and Explanation

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The status of 'dirty' bit in cache indicates:

A. Clean data

B. Shared data

C. Modified data needing write-back

D. Invalid entry

Answer: Option C

Solution (By JKSSB Mock Tests)

For write-back policy.

This question belongs to: Computer CPU (Central Processing Unit)

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Question #1

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Which is a benefit of multi-chip module (MCM) design?

A. Higher single-thread latency

B. Reduced core communication

C. Better binning and cost efficiency

D. Simpler cooling

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Correct Answer: Option C

Explanation:
Used in many modern high-core CPUs.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2

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The physical register file is used in:

A. Register renaming implementations

B. Basic scalar processors

C. No modern CPU

D. Memory controllers

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Correct Answer: Option A

Explanation:
Larger than architectural registers.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3

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The latency of L1 cache is typically:

A. Hundreds of cycles

B. Few clock cycles

C. Infinite

D. Same as RAM

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Correct Answer: Option B

Explanation:
Very low latency for fast access.

This question belongs to: Computer CPU (Central Processing Unit)

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