CPU (Central Processing Unit) MCQs

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CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327
Total Questions

Practice Questions

Page 14 of 17
Question #261
Flag register is also called:
A. Program Counter
B. Status Register or EFLAGS
C. Stack Pointer
D. Accumulator
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Correct Answer: Option B

Explanation:
Contains condition codes.
This question belongs to: Computer CPU (Central Processing Unit)
Question #262
Turbo Boost in Intel CPUs allows:
A. Automatic frequency increase under load
B. Cache reduction
C. Frequency decrease
D. Core disabling
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Correct Answer: Option A

Explanation:
Within power and thermal limits.
This question belongs to: Computer CPU (Central Processing Unit)
Question #263
The decode unit converts:
A. Addresses to data
B. Results to output
C. High-level code
D. Machine code to internal micro-ops
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Correct Answer: Option D

Explanation:
Prepares for execution.
This question belongs to: Computer CPU (Central Processing Unit)
Question #264
Which is a disadvantage of very deep pipelines?
A. Lower clock speeds
B. Simpler hazard detection
C. Higher branch misprediction penalty
D. Reduced power
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Correct Answer: Option C

Explanation:
More stages to flush.
This question belongs to: Computer CPU (Central Processing Unit)
Question #265
The memory ordering model in x86 is:
A. ARM style
B. Strongly ordered with some relaxations
C. No ordering
D. Weakly ordered always
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Correct Answer: Option B

Explanation:
Ensures consistency.
This question belongs to: Computer CPU (Central Processing Unit)
Question #266
Precision Boost Overdrive (PBO) is an AMD feature for:
A. Power saving
B. Aggressive automatic overclocking
C. Core parking
D. Cache clearing
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Correct Answer: Option B

Explanation:
Uses extra power headroom.
This question belongs to: Computer CPU (Central Processing Unit)
Question #267
The branch target buffer (BTB) stores:
A. Data values
B. Instruction opcodes
C. Addresses of taken branches
D. Status flags
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Correct Answer: Option C

Explanation:
For faster branch prediction.
This question belongs to: Computer CPU (Central Processing Unit)
Question #268
Which unit performs logical operations like AND, OR?
A. ALU
B. CU only
C. Register file
D. Cache controller
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Correct Answer: Option A

Explanation:
Part of arithmetic logic capabilities.
This question belongs to: Computer CPU (Central Processing Unit)
Question #269
SoC stands for:
A. System on Chip
B. Single Operation Core
C. System on Cache
D. Secure Operation Channel
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Correct Answer: Option A

Explanation:
Integrates CPU, GPU, etc.
This question belongs to: Computer CPU (Central Processing Unit)
Question #270
The issue width determines:
A. Cache associativity
B. TDP rating
C. How many instructions can be issued per cycle
D. Memory size
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Correct Answer: Option C

Explanation:
Key superscalar parameter.
This question belongs to: Computer CPU (Central Processing Unit)
Question #271
Guard pages and stack canaries are:
A. Power features
B. Hardware only
C. Unrelated to CPU
D. Software security features supported by CPU
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Correct Answer: Option D

Explanation:
Prevent exploits.
This question belongs to: Computer CPU (Central Processing Unit)
Question #272
The L2 cache is typically:
A. Per-core private cache
B. Fully shared
C. Instruction only
D. Slower than L1
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Correct Answer: Option A

Explanation:
Balances speed and size.
This question belongs to: Computer CPU (Central Processing Unit)
Question #273
Which company uses 'Golden Cove' architecture?
A. Intel
B. Apple
C. ARM
D. AMD
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Correct Answer: Option A

Explanation:
Part of recent Intel cores.
This question belongs to: Computer CPU (Central Processing Unit)
Question #274
Return stack buffer helps predict:
A. Data loads
B. ALU results
C. Cache hits
D. Function returns accurately
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Correct Answer: Option D

Explanation:
For CALL/RET pairs.
This question belongs to: Computer CPU (Central Processing Unit)
Question #275
The von Neumann model uses:
A. Quantum bits
B. Separate data buses only
C. Stored program concept
D. No memory
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Correct Answer: Option C

Explanation:
Instructions and data in same memory.
This question belongs to: Computer CPU (Central Processing Unit)
Question #276
FMA instruction stands for:
A. Fast Memory Access
B. Fetch Memory Address
C. Flag Management Algorithm
D. Fused Multiply-Add
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Correct Answer: Option D

Explanation:
Performs multiplication and addition in one step.
This question belongs to: Computer CPU (Central Processing Unit)
Question #277
Which is essential for virtualization?
A. Hardware-assisted virtualization extensions
B. Basic ALU
C. Small cache
D. Low core count
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Correct Answer: Option A

Explanation:
Like VT-x or AMD-V.
This question belongs to: Computer CPU (Central Processing Unit)
Question #278
The pipeline stall due to structural hazard happens when:
A. Branch taken
B. Two instructions need the same hardware resource
C. Cache miss
D. Data dependency
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Correct Answer: Option B

Explanation:
Resource conflict.
This question belongs to: Computer CPU (Central Processing Unit)
Question #279
Apple's Firestorm cores are part of:
A. GPU only
B. M-series ARM-based CPUs
C. x86 processors
D. Server chips
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Correct Answer: Option B

Explanation:
High performance mobile/desktop SoCs.
This question belongs to: Computer CPU (Central Processing Unit)
Question #280
The data cache (D-cache) handles:
A. ALU internal
B. Control signals
C. Instruction fetch
D. Load and store operations
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Correct Answer: Option D

Explanation:
Separate from I-cache.
This question belongs to: Computer CPU (Central Processing Unit)

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