CPU (Central Processing Unit) MCQs

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CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327
Total Questions

Practice Questions

Page 15 of 17
Question #281
Which metric combines clock speed and IPC?
A. Cache hit rate
B. Overall performance in benchmarks
C. TDP only
D. Core temperature
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Correct Answer: Option B

Explanation:
Determines effective speed.
This question belongs to: Computer CPU (Central Processing Unit)
Question #282
The shadow stack is a security feature for:
A. Power management
B. Protecting return addresses
C. Cache protection
D. Data encryption
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Correct Answer: Option B

Explanation:
Against ROP attacks.
This question belongs to: Computer CPU (Central Processing Unit)
Question #283
Multi-level cache hierarchy reduces:
A. Clock frequency
B. Core count
C. Average memory access time
D. Instruction set
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Correct Answer: Option C

Explanation:
Exploits locality.
This question belongs to: Computer CPU (Central Processing Unit)
Question #284
The control bus carries:
A. Signals like read/write, interrupt
B. Memory addresses
C. Data values
D. ALU operands
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Correct Answer: Option A

Explanation:
Commands and status.
This question belongs to: Computer CPU (Central Processing Unit)
Question #285
Zen architecture introduced significant improvements in:
A. Single core legacy
B. IPC and cache subsystem
C. Only clock speed
D. Mobile power
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Correct Answer: Option B

Explanation:
AMD's modern core design.
This question belongs to: Computer CPU (Central Processing Unit)
Question #286
The instruction window in out-of-order CPUs refers to:
A. Fetch buffer
B. Set of instructions being considered for execution
C. Retirement queue
D. Cache lines
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Correct Answer: Option B

Explanation:
For scheduling.
This question belongs to: Computer CPU (Central Processing Unit)
Question #287
Which is a common mobile CPU series?
A. AMD Threadripper
B. Qualcomm Snapdragon
C. EPYC
D. Intel Core i9
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Correct Answer: Option B

Explanation:
ARM-based for smartphones.
This question belongs to: Computer CPU (Central Processing Unit)
Question #288
The bypass network in pipeline is for:
A. Flushing
B. Decoding
C. Stalling pipeline
D. Forwarding results directly
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Correct Answer: Option D

Explanation:
Avoids data hazards.
This question belongs to: Computer CPU (Central Processing Unit)
Question #289
Secure Boot is supported by CPU through:
A. Cache encryption
B. ALU modifications
C. Hardware root of trust
D. Software only
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Correct Answer: Option C

Explanation:
Like TPM integration.
This question belongs to: Computer CPU (Central Processing Unit)
Question #290
The associativity in cache means:
A. Size of cache
B. Number of places a block can go
C. Speed of access
D. Write policy
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Correct Answer: Option B

Explanation:
Affects conflict misses.
This question belongs to: Computer CPU (Central Processing Unit)
Question #291
Which generation of Ryzen uses chiplet design extensively?
A. First generation only
B. Mobile only
C. Ryzen 5000 and later
D. Intel equivalent
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Correct Answer: Option C

Explanation:
For scalability.
This question belongs to: Computer CPU (Central Processing Unit)
Question #292
The exception handling in CPU involves:
A. Precise interrupts and state saving
B. ALU reset
C. Ignoring errors
D. Cache flush only
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Correct Answer: Option A

Explanation:
For errors and interrupts.
This question belongs to: Computer CPU (Central Processing Unit)
Question #293
Graphene or future materials may impact:
A. Software
B. Cooling only
C. Current designs
D. Transistor technology beyond silicon
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Correct Answer: Option D

Explanation:
Potential for better performance.
This question belongs to: Computer CPU (Central Processing Unit)
Question #294
The loop stream detector:
A. Manages power
B. Detects cache misses
C. Handles branches
D. Recognizes and optimizes small loops
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Correct Answer: Option D

Explanation:
Reduces front-end power.
This question belongs to: Computer CPU (Central Processing Unit)
Question #295
Which is true about embedded CPUs?
A. Focus on real-time response and low power
B. High performance gaming
C. Many threads
D. Large cache priority
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Correct Answer: Option A

Explanation:
Used in IoT and appliances.
This question belongs to: Computer CPU (Central Processing Unit)
Question #296
The architectural registers are:
A. Memory locations
B. Visible to software
C. Cache lines
D. Hidden physical only
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Correct Answer: Option B

Explanation:
Part of ISA.
This question belongs to: Computer CPU (Central Processing Unit)
Question #297
Intel's EMIB technology is for:
A. Efficient chiplet packaging
B. Power delivery
C. Software emulation
D. Graphics only
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Correct Answer: Option A

Explanation:
Embedded Multi-Die Interconnect Bridge.
This question belongs to: Computer CPU (Central Processing Unit)
Question #298
A higher clock speed with lower IPC may perform:
A. Always better
B. Same as low clock high IPC
C. Differently depending on workload
D. Worse always
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Correct Answer: Option C

Explanation:
Balance is key.
This question belongs to: Computer CPU (Central Processing Unit)
Question #299
The vector mask in AVX allows:
A. Scalar only
B. No operations
C. Address masking
D. Conditional execution in SIMD
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Correct Answer: Option D

Explanation:
Efficient for predicated operations.
This question belongs to: Computer CPU (Central Processing Unit)
Question #300
Which feature allows dynamic core frequency adjustment?
A. Fixed frequency
B. SpeedStep or Cool'n'Quiet
C. No adjustment
D. Static voltage
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Correct Answer: Option B

Explanation:
Intel and AMD power management.
This question belongs to: Computer CPU (Central Processing Unit)

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