CPU (Central Processing Unit) MCQs

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CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327
Total Questions

Practice Questions

Page 13 of 17
Question #241
The commit stage is also called:
A. Fetch stage
B. Retirement stage
C. Execute stage
D. Decode stage
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Correct Answer: Option B

Explanation:
It finalizes instruction effects.
This question belongs to: Computer CPU (Central Processing Unit)
Question #242
3D stacking in CPUs improves:
A. Manufacturing simplicity
B. Clock speed only
C. Cache density and bandwidth
D. Power consumption negatively
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Correct Answer: Option C

Explanation:
Like AMD's 3D V-Cache.
This question belongs to: Computer CPU (Central Processing Unit)
Question #243
A scoreboard is used for:
A. Dynamic instruction scheduling
B. Cache management
C. Static scheduling
D. Interrupt priority
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Correct Answer: Option A

Explanation:
Tracks dependencies in older designs.
This question belongs to: Computer CPU (Central Processing Unit)
Question #244
The physical register file is used in:
A. Register renaming implementations
B. Basic scalar processors
C. No modern CPU
D. Memory controllers
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Correct Answer: Option A

Explanation:
Larger than architectural registers.
This question belongs to: Computer CPU (Central Processing Unit)
Question #245
Which is a common cause of CPU stalls?
A. More cores
B. Cache miss or branch misprediction
C. Larger cache
D. High clock speed
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Correct Answer: Option B

Explanation:
Both increase pipeline bubbles.
This question belongs to: Computer CPU (Central Processing Unit)
Question #246
The bus cycle includes:
A. Address, data, and control phases
B. ALU operations only
C. Register transfer
D. Instruction decode
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Correct Answer: Option A

Explanation:
For communication with memory.
This question belongs to: Computer CPU (Central Processing Unit)
Question #247
Intel's Alder Lake introduced:
A. First multi-core
B. No efficiency cores
C. Only high power cores
D. Hybrid big.LITTLE architecture in x86
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Correct Answer: Option D

Explanation:
Performance and efficiency cores.
This question belongs to: Computer CPU (Central Processing Unit)
Question #248
The carry flag is set during:
A. Signed overflow
B. Unsigned arithmetic overflow
C. Zero result
D. Negative numbers
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Correct Answer: Option B

Explanation:
Important for multi-precision arithmetic.
This question belongs to: Computer CPU (Central Processing Unit)
Question #249
VLIW architecture relies on:
A. Compiler to pack multiple operations
B. No parallelism
C. Dynamic execution
D. Hardware scheduling only
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Correct Answer: Option A

Explanation:
Very Long Instruction Word.
This question belongs to: Computer CPU (Central Processing Unit)
Question #250
Which helps mitigate Spectre attacks?
A. Hardware fences and speculation barriers
B. More cores
C. Higher TDP
D. Larger cache
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Correct Answer: Option A

Explanation:
Processor and OS level mitigations.
This question belongs to: Computer CPU (Central Processing Unit)
Question #251
The execution port in CPU dispatches to:
A. Control signals
B. Memory only
C. Different functional units
D. Fetch unit
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Correct Answer: Option C

Explanation:
For parallel execution.
This question belongs to: Computer CPU (Central Processing Unit)
Question #252
AMD's Infinity Fabric is a:
A. Instruction decoder
B. Power delivery system
C. Cache protocol
D. High-speed interconnect for chiplets
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Correct Answer: Option D

Explanation:
Enables communication between dies.
This question belongs to: Computer CPU (Central Processing Unit)
Question #253
The pipeline depth affects:
A. Core count
B. Cache size
C. TDP only
D. Frequency potential and hazard complexity
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Correct Answer: Option D

Explanation:
Deeper pipelines allow higher clocks but more hazards.
This question belongs to: Computer CPU (Central Processing Unit)
Question #254
Which is not a type of cache mapping?
A. Direct mapped, set associative, fully associative
B. None of the above
C. Physical only
D. Virtual mapped
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Correct Answer: Option D

Explanation:
Standard techniques are the three listed.
This question belongs to: Computer CPU (Central Processing Unit)
Question #255
The vector register file supports:
A. Status flags
B. Scalar operations only
C. Address storage
D. SIMD operations with multiple elements
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Correct Answer: Option D

Explanation:
For parallel data processing.
This question belongs to: Computer CPU (Central Processing Unit)
Question #256
Core parking is a power management feature that:
A. Increases voltage
B. Clears cache
C. Overclocks active cores
D. Puts idle cores into sleep state
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Correct Answer: Option D

Explanation:
Saves energy.
This question belongs to: Computer CPU (Central Processing Unit)
Question #257
The ITLB caches:
A. Instruction address translations
B. ALU results
C. Branch history
D. Data translations
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Correct Answer: Option A

Explanation:
Separate from DTLB.
This question belongs to: Computer CPU (Central Processing Unit)
Question #258
Which extension provides hardware encryption acceleration?
A. AES-NI
B. AVX only
C. SSE4
D. FMA
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Correct Answer: Option A

Explanation:
Speeds up AES algorithms.
This question belongs to: Computer CPU (Central Processing Unit)
Question #259
In-order execution processors are simpler but may have:
A. No pipeline
B. Higher complexity
C. Always better performance
D. Lower IPC in some workloads
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Correct Answer: Option D

Explanation:
Due to stalls on dependencies.
This question belongs to: Computer CPU (Central Processing Unit)
Question #260
The mesh interconnect is used in:
A. GPUs exclusively
B. Low power mobiles
C. High core count Intel CPUs
D. Embedded systems only
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Correct Answer: Option C

Explanation:
Scalable for many cores.
This question belongs to: Computer CPU (Central Processing Unit)

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