CPU (Central Processing Unit) MCQs

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CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327
Total Questions

Practice Questions

Page 12 of 17
Question #221
The load/store architecture restricts memory access to:
A. All instructions
B. ALU only
C. Control unit
D. Dedicated load and store instructions
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Correct Answer: Option D

Explanation:
Typical in RISC designs.
This question belongs to: Computer CPU (Central Processing Unit)
Question #222
Hyper-threading is Intel's implementation of:
A. Multi-core
B. Simultaneous Multithreading
C. Cache prefetch
D. Overclocking
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Correct Answer: Option B

Explanation:
It presents one core as multiple logical processors.
This question belongs to: Computer CPU (Central Processing Unit)
Question #223
Which cache level is usually smallest and fastest?
A. L3 Cache
B. L4 Cache
C. L1 Cache
D. L2 Cache
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Correct Answer: Option C

Explanation:
Split into instruction and data caches per core.
This question belongs to: Computer CPU (Central Processing Unit)
Question #224
The opcode fetch is part of:
A. Instruction fetch stage
B. Execution stage
C. Write-back stage
D. Memory stage
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Correct Answer: Option A

Explanation:
First step in processing an instruction.
This question belongs to: Computer CPU (Central Processing Unit)
Question #225
EPIC architecture was used in:
A. Modern x86
B. Embedded controllers
C. Intel Itanium processors
D. ARM mobiles
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Correct Answer: Option C

Explanation:
Explicitly Parallel Instruction Computing.
This question belongs to: Computer CPU (Central Processing Unit)
Question #226
A CPU's TDP rating indicates:
A. Thread Distribution Protocol
B. Total Data Processed
C. Thermal Design Power
D. Transistor Density Parameter
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Correct Answer: Option C

Explanation:
Maximum heat output under sustained load.
This question belongs to: Computer CPU (Central Processing Unit)
Question #227
Register renaming solves:
A. Cache misses
B. Write-after-read and write-after-write hazards
C. Control hazards
D. Interrupt handling
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Correct Answer: Option B

Explanation:
It eliminates false dependencies.
This question belongs to: Computer CPU (Central Processing Unit)
Question #228
The base clock (BCLK) in Intel systems affects:
A. Only GPU
B. Storage speed
C. CPU, memory, and bus frequencies
D. Network interface
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Correct Answer: Option C

Explanation:
It is the reference frequency.
This question belongs to: Computer CPU (Central Processing Unit)
Question #229
Which is a benefit of multi-chip module (MCM) design?
A. Reduced core communication
B. Higher single-thread latency
C. Better binning and cost efficiency
D. Simpler cooling
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Correct Answer: Option C

Explanation:
Used in many modern high-core CPUs.
This question belongs to: Computer CPU (Central Processing Unit)
Question #230
The zero flag is set when:
A. Overflow happens
B. Carry occurs
C. Negative result
D. Result of operation is zero
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Correct Answer: Option D

Explanation:
Useful for conditional branching.
This question belongs to: Computer CPU (Central Processing Unit)
Question #231
NPU in modern processors accelerates:
A. Storage access
B. Basic integer math
C. Graphics rendering
D. Neural network and AI computations
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Correct Answer: Option D

Explanation:
Dedicated for machine learning tasks.
This question belongs to: Computer CPU (Central Processing Unit)
Question #232
Instruction fusion combines:
A. Multiple instructions into one micro-op
B. Caches
C. Buses
D. Cores
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Correct Answer: Option A

Explanation:
Improves decode and execution efficiency.
This question belongs to: Computer CPU (Central Processing Unit)
Question #233
Which architecture uses condition codes extensively?
A. Many RISC designs
B. Only CISC
C. No modern CPU
D. Quantum processors
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Correct Answer: Option A

Explanation:
Flags guide conditional execution.
This question belongs to: Computer CPU (Central Processing Unit)
Question #234
The ring interconnect is used in:
A. Intel CPUs for core communication
B. External I/O
C. Memory access only
D. Power delivery
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Correct Answer: Option A

Explanation:
Provides high bandwidth between cores.
This question belongs to: Computer CPU (Central Processing Unit)
Question #235
Overclocking primarily increases:
A. Cache size
B. Number of cores
C. Memory capacity
D. Clock frequency beyond stock
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Correct Answer: Option D

Explanation:
Requires better cooling and stability testing.
This question belongs to: Computer CPU (Central Processing Unit)
Question #236
The microcode ROM is part of:
A. ALU
B. Control Unit in CISC processors
C. Registers
D. Cache
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Correct Answer: Option B

Explanation:
It translates complex instructions.
This question belongs to: Computer CPU (Central Processing Unit)
Question #237
Which feature is important for server CPUs?
A. Low power mobile focus
B. High core count and ECC memory support
C. Integrated graphics priority
D. Gaming optimizations only
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Correct Answer: Option B

Explanation:
Reliability and scalability.
This question belongs to: Computer CPU (Central Processing Unit)
Question #238
The store buffer holds:
A. Fetched instructions
B. Branch targets
C. Data waiting to be written to memory
D. Decoded uops
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Correct Answer: Option C

Explanation:
It allows execution to continue.
This question belongs to: Computer CPU (Central Processing Unit)
Question #239
Big.LITTLE processing is a form of:
A. Asymmetric multi-processing
B. Symmetric only
C. Single core
D. No power management
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Correct Answer: Option A

Explanation:
Mix of high-performance and efficient cores.
This question belongs to: Computer CPU (Central Processing Unit)
Question #240
Which instruction set supports 256-bit vectors?
A. x87
B. AVX2
C. MMX
D. SSE only
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Correct Answer: Option B

Explanation:
Advanced Vector Extensions 2.
This question belongs to: Computer CPU (Central Processing Unit)

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