CPU (Central Processing Unit) MCQs

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CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327
Total Questions

Practice Questions

Page 10 of 17
Question #181
The Harvard architecture differs from von Neumann by having:
A. Slower processing
B. No registers
C. Shared memory only
D. Separate buses and memory for instructions and data
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Correct Answer: Option D

Explanation:
This allows simultaneous instruction fetch and data access.
This question belongs to: Computer CPU (Central Processing Unit)
Question #182
What does the acronym FPU stand for in CPU context?
A. Floating Point Unit
B. Fast Processing Unit
C. Flag Processing Unit
D. Fetch Pipeline Unit
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Correct Answer: Option A

Explanation:
FPU handles floating-point arithmetic operations.
This question belongs to: Computer CPU (Central Processing Unit)
Question #183
Branch misprediction leads to:
A. Increased clock speed
B. Pipeline flush and performance loss
C. Reduced power consumption
D. Better cache hit rate
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Correct Answer: Option B

Explanation:
Wrong prediction requires discarding speculative work.
This question belongs to: Computer CPU (Central Processing Unit)
Question #184
L3 cache is typically:
A. Slower than registers but faster than RAM
B. Used only for instructions
C. Private to each core
D. Shared among all CPU cores
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Correct Answer: Option D

Explanation:
It acts as a larger shared cache layer.
This question belongs to: Computer CPU (Central Processing Unit)
Question #185
The Memory Management Unit (MMU) is responsible for:
A. Instruction decoding
B. Arithmetic calculations
C. Virtual to physical address translation
D. Power management
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Correct Answer: Option C

Explanation:
MMU handles memory protection and address mapping.
This question belongs to: Computer CPU (Central Processing Unit)
Question #186
Which of the following is a CISC characteristic?
A. Large number of registers
B. Fixed length instructions
C. Simple pipeline
D. Complex multi-cycle instructions
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Correct Answer: Option D

Explanation:
CISC instructions can perform multiple low-level operations.
This question belongs to: Computer CPU (Central Processing Unit)
Question #187
SIMD stands for:
A. Sequential Instruction Multiple Decode
B. System Integrated Memory Device
C. Shared Instruction Memory Data
D. Single Instruction Multiple Data
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Correct Answer: Option D

Explanation:
SIMD allows one instruction to process multiple data elements.
This question belongs to: Computer CPU (Central Processing Unit)
Question #188
The purpose of a TLB is to:
A. Control ALU operations
B. Manage interrupts
C. Cache recent virtual-to-physical address mappings
D. Store temporary data
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Correct Answer: Option C

Explanation:
TLB speeds up address translation.
This question belongs to: Computer CPU (Central Processing Unit)
Question #189
In pipelined processors, a data hazard occurs when:
A. Cache miss happens
B. Branches are predicted wrong
C. Clock speed is too high
D. An instruction depends on the result of a previous instruction still in pipeline
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Correct Answer: Option D

Explanation:
Forwarding or stalls are used to resolve them.
This question belongs to: Computer CPU (Central Processing Unit)
Question #190
Which technology allows a single physical core to execute two threads?
A. Multi-core processing
B. Overclocking
C. Simultaneous Multithreading (SMT)
D. Cache coherence
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Correct Answer: Option C

Explanation:
SMT improves resource utilization.
This question belongs to: Computer CPU (Central Processing Unit)
Question #191
The term 'process node' like 5nm refers to:
A. Clock frequency
B. Semiconductor manufacturing technology
C. Cache size
D. Number of CPU cores
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Correct Answer: Option B

Explanation:
Smaller nodes improve density and efficiency.
This question belongs to: Computer CPU (Central Processing Unit)
Question #192
Which bus carries memory addresses from CPU?
A. Control Bus
B. Address Bus
C. System Bus
D. Data Bus
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Correct Answer: Option B

Explanation:
Address bus specifies memory locations.
This question belongs to: Computer CPU (Central Processing Unit)
Question #193
Out-of-order execution primarily helps overcome:
A. Power constraints
B. Control flow changes
C. Data dependencies and stalls
D. Memory capacity limits
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Correct Answer: Option C

Explanation:
It reorders instructions for better throughput.
This question belongs to: Computer CPU (Central Processing Unit)
Question #194
The accumulator register is most commonly associated with:
A. Storing ALU operation results
B. Managing stack operations
C. Storing status flags
D. Holding instruction addresses
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Correct Answer: Option A

Explanation:
It serves as a default destination for results.
This question belongs to: Computer CPU (Central Processing Unit)
Question #195
Chiplet-based CPU design offers advantages in:
A. Cost, yield, and scalability
B. Lower power always
C. Simpler manufacturing
D. Single die performance only
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Correct Answer: Option A

Explanation:
Multiple smaller dies are connected.
This question belongs to: Computer CPU (Central Processing Unit)
Question #196
Which flag indicates arithmetic overflow?
A. Zero flag
B. Overflow flag
C. Carry flag
D. Sign flag
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Correct Answer: Option B

Explanation:
It signals when a result exceeds representable range.
This question belongs to: Computer CPU (Central Processing Unit)
Question #197
RISC-V is an example of:
A. Memory controller
B. Graphics processor
C. Open-source Instruction Set Architecture
D. Proprietary CISC design
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Correct Answer: Option C

Explanation:
It is a royalty-free RISC ISA.
This question belongs to: Computer CPU (Central Processing Unit)
Question #198
The write-back cache policy updates main memory:
A. Immediately on every write
B. Only on read
C. Never
D. When the cache line is evicted
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Correct Answer: Option D

Explanation:
It minimizes memory traffic.
This question belongs to: Computer CPU (Central Processing Unit)
Question #199
Superscalar processors can issue:
A. Instructions out of order only
B. No instructions
C. One instruction only
D. Multiple instructions per clock cycle
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Correct Answer: Option D

Explanation:
They have multiple execution units.
This question belongs to: Computer CPU (Central Processing Unit)
Question #200
Which component manages interrupt requests in CPU?
A. Registers only
B. Control Unit
C. ALU
D. Cache controller
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Correct Answer: Option B

Explanation:
It saves context and transfers control to ISR.
This question belongs to: Computer CPU (Central Processing Unit)

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