CPU (Central Processing Unit) MCQs

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CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

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Total Questions

Practice Questions

Page 4 of 17
Question #61
Speculative execution in CPU:
A. Waits for all conditions
B. Increases latency
C. Executes instructions before knowing if needed
D. Reduces cores
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Correct Answer: Option C

Explanation:
It improves performance but can have security implications like Spectre.
This question belongs to: Computer CPU (Central Processing Unit)
Question #62
The width of the data bus affects:
A. Instruction complexity
B. How much data can be transferred at once
C. Addressable memory
D. Clock speed only
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Correct Answer: Option B

Explanation:
Wider bus allows more parallel data transfer.
This question belongs to: Computer CPU (Central Processing Unit)
Question #63
Which component is responsible for instruction sequencing?
A. I/O ports
B. ALU
C. Cache
D. Program Counter in CU
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Correct Answer: Option D

Explanation:
Program Counter manages the sequence of instruction fetch.
This question belongs to: Computer CPU (Central Processing Unit)
Question #64
L1 cache is:
A. Slower than L2
B. Closest and fastest cache to CPU core
C. Part of main memory
D. Shared among all cores
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Correct Answer: Option B

Explanation:
L1 cache provides the quickest access for each core.
This question belongs to: Computer CPU (Central Processing Unit)
Question #65
The term 'CPU throttling' refers to:
A. Increasing speed
B. Changing architecture
C. Adding more cores
D. Reducing clock speed to manage heat
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Correct Answer: Option D

Explanation:
Dynamic frequency scaling to control temperature and power.
This question belongs to: Computer CPU (Central Processing Unit)
Question #66
Address bus width determines:
A. Maximum addressable memory
B. Data transfer rate
C. ALU operations
D. Clock frequency
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Correct Answer: Option A

Explanation:
More address lines allow accessing larger memory space.
This question belongs to: Computer CPU (Central Processing Unit)
Question #67
In Harvard architecture, there are:
A. Shared memory
B. Only registers
C. Separate memories for instructions and data
D. No memory
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Correct Answer: Option C

Explanation:
It allows simultaneous access to instructions and data.
This question belongs to: Computer CPU (Central Processing Unit)
Question #68
The accumulator is often used in:
A. No operations
B. Implicit addressing
C. All operations equally
D. Memory management
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Correct Answer: Option B

Explanation:
Many instructions implicitly use the accumulator.
This question belongs to: Computer CPU (Central Processing Unit)
Question #69
Quantum processors differ from classical CPUs by using:
A. Same ALU
B. Qubits
C. Slower speed
D. Bits
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Correct Answer: Option B

Explanation:
They leverage quantum mechanics for certain computations.
This question belongs to: Computer CPU (Central Processing Unit)
Question #70
Which is not a function of the Control Unit?
A. Generating timing signals
B. Instruction decoding
C. Managing data flow
D. Performing division
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Correct Answer: Option D

Explanation:
Arithmetic operations like division are handled by ALU.
This question belongs to: Computer CPU (Central Processing Unit)
Question #71
Benchmarking tools measure CPU performance in terms of:
A. Battery life
B. Screen resolution
C. Storage in GB
D. FLOPS or MIPS
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Correct Answer: Option D

Explanation:
Floating Point Operations Per Second or Million Instructions Per Second.
This question belongs to: Computer CPU (Central Processing Unit)
Question #72
The front side bus (FSB) connects:
A. CPU to chipset/memory
B. ALU to CU
C. Registers internally
D. GPU only
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Correct Answer: Option A

Explanation:
It is the data pathway between processor and other components.
This question belongs to: Computer CPU (Central Processing Unit)
Question #73
Overclocking a CPU means:
A. Disabling cores
B. Adding software
C. Running at lower speed
D. Running at higher than rated clock speed
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Correct Answer: Option D

Explanation:
It increases performance but risks stability and heat.
This question belongs to: Computer CPU (Central Processing Unit)
Question #74
Which register holds the current instruction's operands address?
A. Instruction Register
B. Memory Address Register
C. Program Counter
D. Status Register
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Correct Answer: Option B

Explanation:
MAR is used for memory access addresses.
This question belongs to: Computer CPU (Central Processing Unit)
Question #75
ARM processors are commonly used in:
A. Desktop only
B. High power servers only
C. Mobile devices due to power efficiency
D. No devices
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Correct Answer: Option C

Explanation:
They are known for low power consumption.
This question belongs to: Computer CPU (Central Processing Unit)
Question #76
The write-back cache policy:
A. Writes data to memory immediately
B. Reads only
C. Delays write to memory until needed
D. Never writes
Discuss
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Correct Answer: Option C

Explanation:
It improves performance by reducing memory writes.
This question belongs to: Computer CPU (Central Processing Unit)
Question #77
Instruction level parallelism (ILP) is exploited by:
A. Pipelining and superscalar designs
B. Memory
C. Software only
D. Single core only
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Correct Answer: Option A

Explanation:
Hardware techniques maximize parallel instruction execution.
This question belongs to: Computer CPU (Central Processing Unit)
Question #78
A CPU with integrated graphics has:
A. No display capability
B. Separate GPU
C. GPU on the same die
D. Only CPU functions
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Correct Answer: Option C

Explanation:
APUs or processors with iGPU combine CPU and graphics.
This question belongs to: Computer CPU (Central Processing Unit)
Question #79
The main bottleneck in many systems is:
A. ALU only
B. Memory access speed (von Neumann bottleneck)
C. Registers
D. CPU speed always
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Correct Answer: Option B

Explanation:
Shared memory access can limit performance.
This question belongs to: Computer CPU (Central Processing Unit)
Question #80
Which of the following enhances CPU performance without changing architecture?
A. Removing ALU
B. Lowering voltage
C. Increasing cache size
D. Decreasing registers
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Correct Answer: Option C

Explanation:
Larger cache reduces memory access latency.
This question belongs to: Computer CPU (Central Processing Unit)

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