CPU (Central Processing Unit) MCQs

Computer

CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327
Total Questions

Practice Questions

Page 7 of 17
Question #121
Which technique reduces branch misprediction penalty?
A. Branch prediction and speculative execution
B. Fewer registers
C. No prediction
D. Slower clock
Discuss
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Correct Answer: Option A

Explanation:
Modern CPUs use advanced predictors.
This question belongs to: Computer CPU (Central Processing Unit)
Question #122
EPYC processors are designed for:
A. Basic desktops
B. Smartphones
C. Toys
D. Servers and data centers
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Correct Answer: Option D

Explanation:
AMD's server CPU line.
This question belongs to: Computer CPU (Central Processing Unit)
Question #123
The reorder buffer in out-of-order CPUs helps maintain:
A. Program order for retirement
B. Faster fetch
C. ALU speed
D. Memory size
Discuss
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Correct Answer: Option A

Explanation:
Ensures correct sequential appearance of results.
This question belongs to: Computer CPU (Central Processing Unit)
Question #124
Neural Processing Unit (NPU) in CPUs is for:
A. Accelerating AI and machine learning tasks
B. Storage
C. Display
D. Basic arithmetic
Discuss
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Correct Answer: Option A

Explanation:
Specialized for tensor operations in AI.
This question belongs to: Computer CPU (Central Processing Unit)
Question #125
Which is a measure of CPU efficiency?
A. Color of chip
B. Size of case
C. Number of fans
D. Performance per watt
Discuss
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Correct Answer: Option D

Explanation:
Important for mobile and data center applications.
This question belongs to: Computer CPU (Central Processing Unit)
Question #126
The translation lookaside buffer (TLB) caches:
A. Instructions
B. Data values
C. Control signals
D. Virtual to physical address translations
Discuss
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Correct Answer: Option D

Explanation:
Speeds up memory address translation.
This question belongs to: Computer CPU (Central Processing Unit)
Question #127
Apple Silicon like M-series uses:
A. ARM-based architecture
B. x86 only
C. CISC heavy
D. No CPU
Discuss
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Correct Answer: Option A

Explanation:
Custom ARM chips for Macs.
This question belongs to: Computer CPU (Central Processing Unit)
Question #128
Simultaneous Multithreading (SMT) is known as:
A. Cache only
B. Power saving
C. Single threading
D. Hyper-threading in Intel
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Correct Answer: Option D

Explanation:
Allows multiple threads per physical core.
This question belongs to: Computer CPU (Central Processing Unit)
Question #129
The critical path in CPU design determines:
A. The maximum clock frequency
B. Memory size
C. Number of pins
D. Color
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Correct Answer: Option A

Explanation:
Longest delay path limits speed.
This question belongs to: Computer CPU (Central Processing Unit)
Question #130
Which is not a CPU performance metric?
A. Power consumption
B. Temperature in Celsius
C. IPC, clock speed, cores
D. Benchmark scores
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Correct Answer: Option B

Explanation:
Temperature is a constraint, not direct performance measure.
This question belongs to: Computer CPU (Central Processing Unit)
Question #131
The memory controller can be:
A. Part of ALU
B. Irrelevant
C. Integrated in the CPU
D. Always external
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Correct Answer: Option C

Explanation:
On-die memory controller reduces latency.
This question belongs to: Computer CPU (Central Processing Unit)
Question #132
Ray tracing acceleration in CPUs/GPUs uses:
A. Specialized hardware units
B. No support
C. Software simulation
D. Basic ALU only
Discuss
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Correct Answer: Option A

Explanation:
Dedicated RT cores or units.
This question belongs to: Computer CPU (Central Processing Unit)
Question #133
Which company developed the x86-64 architecture extension?
A. Qualcomm
B. Intel only
C. ARM
D. AMD
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Correct Answer: Option D

Explanation:
AMD64 extended the original x86.
This question belongs to: Computer CPU (Central Processing Unit)
Question #134
The ROB (Reorder Buffer) size affects:
A. Address bus
B. Cache size
C. Power only
D. How many instructions can be in flight
Discuss
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Correct Answer: Option D

Explanation:
Larger ROB supports more out-of-order execution.
This question belongs to: Computer CPU (Central Processing Unit)
Question #135
Secure enclaves like Intel SGX provide:
A. Slower processing
B. Public data access
C. Protected execution environment
D. No security
Discuss
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Correct Answer: Option C

Explanation:
Isolated from the rest of the system.
This question belongs to: Computer CPU (Central Processing Unit)
Question #136
The fetch width in superscalar CPUs refers to:
A. Cache line
B. Register size
C. Data bus width
D. Number of instructions fetched per cycle
Discuss
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Correct Answer: Option D

Explanation:
Affects instruction throughput.
This question belongs to: Computer CPU (Central Processing Unit)
Question #137
Which of the following is a low-power CPU design focus?
A. Servers exclusively
B. Mobile and embedded systems
C. High performance desktops only
D. Gaming PCs
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Correct Answer: Option B

Explanation:
Emphasis on efficiency for battery life.
This question belongs to: Computer CPU (Central Processing Unit)
Question #138
The rename registers in modern CPUs help avoid:
A. Control hazards
B. Structural hazards only
C. False dependencies (WAR, WAW)
D. True data dependencies
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Correct Answer: Option C

Explanation:
Register renaming for better ILP.
This question belongs to: Computer CPU (Central Processing Unit)
Question #139
TSMC and Samsung are leaders in:
A. Software development
B. Keyboard production
C. Monitor manufacturing
D. CPU chip fabrication
Discuss
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Correct Answer: Option D

Explanation:
Semiconductor foundries.
This question belongs to: Computer CPU (Central Processing Unit)
Question #140
The loop buffer or uop cache stores:
A. Decoded micro-operations for loops
B. Data from memory
C. Addresses
D. Power states
Discuss
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Correct Answer: Option A

Explanation:
Reduces power by avoiding repeated decode.
This question belongs to: Computer CPU (Central Processing Unit)

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